Integrated circuits are chemically and physically integrated into a substrate, such as a silicon or gallium arsenide wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication. Up to a thousand or more devices are formed simultaneously on the surface of a single wafer of semiconductor material.
It is essential for high device yields to start with a flat semiconductor wafer. If the process steps of device fabrication are performed on a wafer surface that is not uniform, various problems can occur which may result in a large number of inoperable devices.
Previous methods used to ensure the wafer surface planarity included forming an oxide such as borophosphosilicate glass (BPSG) layer on the wafer surface, then heating the wafer to reflow and planarize the oxide layer. This “reflow” method of planarizing the wafer surface was sufficient with fairly large device geometries, but as the technology allowed for smaller device feature sizes, this method produced unsatisfactory results.
Another method which has been used to produce a planar wafer surface is to use the oxide reflow method described above, then spin coat the wafer with photoresist. The spin coating of the material on the wafer surface fills the low points and produces a planar surface from which to start. Next, a dry etch, which removes photoresist and oxide at a rate sufficiently close to 1:1, removes the photoresist and the high points of the wafer, thereby producing a planar oxide layer on the wafer surface.
Most recently, chemical mechanical planarization (CMP) processes have been used to planarize the surface of wafers in preparation for device fabrication. The CMP process involves holding a thin flat wafer of semiconductor material against a rotating wetted polishing pad surface under a controlled downward pressure. A polishing slurry such as a mixture of either a basic or acidic solution used as a chemical etch component in combination with alumina or silica particles used as an abrasive etch component may be used. A rotating polishing head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft wetted pad material such as blown polyurethane.
Such apparatus for polishing thin flat semiconductor wafers are well known in the art. U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,031 to Walsh, for instance, disclose such apparatus.
Deposited conductors are an integral part of every integrated circuit, and provide the role of surface wiring for conducting current. Specifically, the deposited conductors are used to wire together the various components that are formed in the surface of the wafer. Electronic devices formed within the wafer have active areas which must be contacted with conductive runners, such as metal. Typically, a layer of insulating material is applied stop the wafer and selectively masked to provide contact opening patterns. The layer is subsequently etched, for instance with a reactive ion etch (RIE), to provide contact openings from the upper surface of the insulating layer down into the wafer to provide electrical contact with selected active areas.
Certain metals and allows deposited by vacuum evaporation and sputtering techniques do not provide the most desired coverage within the contact openings when applied to the surface of a wafer. An example of a metal which typically provides such poor coverage is sputtered aluminum, or alloys of aluminum with silicon and/or copper. One metallization scheme which does provide good coverage within contact vias is tungsten deposited by the chemical vapor deposition (CVD) technique. Tungsten is not, however, as conductive as aluminum. Accordingly, a tungsten layer is typically etched or polished back to provide a plug within the insulation layer, the plug having a flat upper surface which is flush with the surface of the insulator. A layer of aluminum would subsequently be applied atop the wafer surface to contact the plug. The aluminum layer is then selectively etched to provide the desired interconnecting runners coupling the tungsten with other circuitry.
FIG. 1 shows a desirable outcome of a process to produce a tungsten plug. In accordance with wafer fabrication techniques, a material such as an oxide layer 10 covers the material of the wafer surface 12. The tungsten 14 which fills the contact hole 16 in the oxide material 10 is level with the surface of the oxide layer. FIG. 2 illustrates one problem with present methods of tungsten etch backs, an over etching within the contacts which recesses the tungsten 14 within the contact hole 16 in the wafer surface 10. This can provide for poor contact between the tungsten plug 14 with the aluminum or aluminum alloy layer (not shown) which would be subsequently deposited by sputtering. It is difficult to provide reliable contacts between the aluminum and the recessed tungsten plugs which result from conventional tungsten etchback techniques such as reactive ion etching (RIE).
In addition to RIE, another conventional tungsten etch back means includes a single-step CMP etchback using a polishing slurry and polishing pad. A layer of tungsten is formed by CVD or other means onto the wafer surface, thereby filling the contact holes in the insulation layer with tungsten. The surface of the wafer is polished to remove the tungsten overlying the surface of the wafer, which leaves the contact holes filled with tungsten. Due to the chemical nature of the slurry and compressible nature of the polishing pad, a certain amount of the tungsten material is removed from the contact holes, leaving the recessed tungsten structure 14 of FIG. 2.
U.S. Pat. No. 4,992,135 describes a method of etching back tungsten layers, which is incorporated herein by reference.
A need remains for improved methods of etching back tungsten layers on semiconductor wafers to allow for good contact with layers of metal or other conductive material which are subsequently deposited.